This invention relates to central processor units and, in particular, to the use of a single-port Random Access Memory (RAM) that is shared between the Central Processing Unit and a State Machine.
It is a problem in the field of Central Processing Units to balance the cost of memory with the speed of data read/write operations and the ability for multiple processors to access the same data that is stored in the memory. Traditionally, a single-port Random Access Memory is used in a Central Processing Unit environment due to the low cost of such devices when compared with a dual-port Random Access Memory. In addition, the dual-port Random Access Memory requires more pins and consumes more power than the comparable single-port Random Access Memory. However, it is frequently necessary to share the data stored in the single-port Random Access Memory between the Central Processing Unit and a State Machine. The State Machine typically requires a continuous stream of data from the Random Access Memory while the Central Processing Unit read and writes data in the Random Access Memory on a more irregular basis. Therefore, there is a significant impetus to adapt a single-port Random Access Memory for concurrent use by two processing elements.
This is traditionally accomplished by running the single-port Random Access Memory at a higher clock rate than is required by the State Machine and then using the resultant extra clock times for the Central Processing Unit to access the single-port Random Access Memory. The State Machine typically requires a continuous stream of data, read from consecutive addresses, while operating at top speed. When the single-port Random Access Memory can operate at double the speed required by the State Machine, then there is an adequate level of access to the single-port Random Access Memory for the Central Processing Unit. Where the difference between the maximum clock rate of the single-port Random Access Memory and the operating rate of the State Machine is less than the needs of the Central Processing Unit, then this configuration may fail to deliver the required performance.
There have been a number of attempts to address this problem, but they require precise clock synchronization and/or forcing the State Machine into an idle state during Central Processing Unit memory accesses to create available clock cycles for the Central Processing Unit, thereby sharing the performance degradation between the State Machine and the Central Processing Unit.
The above-described problems are solved and a technical advance achieved in the art by the present single-port random access memory equipped with a relief module to operate as a dual-port shared memory (xe2x80x9crelief module equipped random access memoryxe2x80x9d) which avoids the need for enforced idle cycles for the processors, thereby enabling the State Machine to operate at its maximum speed. This relief module equipped random access memory also enables the Central Processing Unit to access the data in the single-port Random Access Memory as required to read and write the data contained therein. This is accomplished by the addition of one or more single-port Random Access Memory modules to the plurality of Random Access Memory modules that are typically specified for a particular application. The extra Random Access Memory module alternates its output with each of the others of the plurality of Random Access Memory modules, on a sequential basis, thereby providing effectively extra clock cycles for each Random Access Memory module. As a result, the shared memory system improves the memory access performance of both the Central Processing Unit and the State Machine.
This circuitry also renders the hardware configuration of Random Access Memory modules with the associated relief Random Access Memory module transparent to the software that executes on the Central Processing Unit. This is due to the fact that both the Central processing Unit and the State Machine perform the same memory address substitutions so the memory accesses are synchronized with respect to the physical memory addresses.